The field of integrated circuitry is a rapidly developing field of technology. The number of integrated circuits per unit of surface area of a substrate on which the integrated circuits are built, referred to as integrated circuit density, is continually increasing. The highest integrated circuit density is achieved using Field Effect Transistors (FETs). An FET is a device having a source, gate, and drain arranged such that when a high logic signal voltage is applied to the gate, current may pass from the source to the drain. Similarly, the FET does not allow current to pass between the source and the drain when a low logic signal is applied to the gate. When the integrated circuit density increases, the amount of power dissipated by the large number of integrated circuits on the substrate is increased. The amount of power dissipation is important because complicated heat sinks and circuit packaging may be required to prevent the chip temperature from rising above a value at which the chip was designed to operate. In addition, many electronic devices containing integrated circuits operate on stored power. For example, portable computers often operate on battery power. When power dissipation increases, the faster the battery wears down and the shorter the usefulness of the electronic device. Therefore, reducing power consumption is important for the design of integrated circuits.
One way to decrease the power consumption per unit area of substrate of the integrated circuit is to reduce the voltage at which the circuits operate. However, decreasing the voltage level at which circuits operate creates a compatibility problem because some integrated circuits are designed to operate at set voltage levels. For example, some circuits with which the low voltage circuits must interact, must operate at high voltage levels in order to operate electromechanical devices. Also, there are many integrated circuits in existence which cannot change or lower their operating voltage and the new lower voltage circuits must interact with them as well. Therefore, in order to lower the voltage of new integrated circuits to dissipate less power, some form of interface circuit must be developed so that the low voltage and low power circuits can interact with the higher voltage circuits.
In general, the prior art has provided a variety of interface circuits for translating lower voltage levels into higher voltage logic levels and vice versa. This is because integrated circuits implementing logic functions have been generally decreasing the logic voltage levels over the history of integrated circuit development. For example, many circuits exist for translating 12 volt logic signals into logic signals compatible with 5 volt logic technology. Transistor to Transistor Logic (TTL) standards exist for the purpose of allowing interfacing of circuits having different logic voltage levels. However, these TTL standards generally only work for circuits using a power supply voltage of 3.3 volts or more. Circuits using such a power supply voltage have a logic signal swing high enough so that the FET logic state for any transistor is well defined.
Leading edge technology requires an interface circuit which translates lower voltage logic levels, such as 2.4 volts, into 3.3 volt logic levels. The 2.4 volt logic levels, which for example are associated with powering an integrated circuit chip from two rechargeable 1.2 volt batteries, are low enough so that individual transistors within an integrated circuit may need to be optimized to work well at the lower voltage. Typically, transistors designed to work with the lower voltages have a lower value of threshold voltage at which the transistor turns on. However, this means that these transistors turn on more easily or are more leaky, especially when interacting with 3.3 volt logic circuitry. This poorly defined FET logic state results in increased power consumption because current is flowing in the FET devices when the design of the circuit calls for current not to be flowing in the FET devices.
FIG. 1 illustrates an example of this prior art problem. FIG. 1 illustrates a prior art voltage interface circuit for translating a 2.4 volt logic level into a 3.3 volt logic level. The low voltage logic 5 has an output 7 which has a high (or 1) logic voltage level of 2.4 volts. The output 7 of the low voltage logic 5 is the input into the gates of transistors 10 and 30 which are part of the interface circuit. Transistor 30 is an N-channel device which turns on (allows current to flow) when the gate voltage is high and transistor 10 is a P-channel device which turns off when the gate voltage is high. When the output 7 of the low voltage logic is high, the input voltage to the gate of transistor 70 (P-channel) is low. In this state, an electrical connection is made between the 3.3 volt power supply and the output of the interface circuit 80 through the P-channel transistors 60 and 70. As a result, the output of the interface circuit 80 rises to a high voltage level. Similarly, when the output 7 of the low voltage logic is low, the gate voltage of N-channel transistor 40 is high, and the interface circuit output 80 is connected to ground and is at a low voltage level.
In this application, the transistors of the interface circuit have been optimized to work with a 2.4 volt power supply. They are made in the same integrated circuit technology as the low voltage circuits, except they are powered with a higher voltage power supply. It is desirable to avoid reliability hazards associated with applying a relatively high voltage to low voltage transistors by limiting the voltage level on these devices to 2.4 volts or less from the gate to source or drain to source. Therefore, transistor 20 is inserted in series with transistors 10 and 30 to act as a diode designed to have a voltage drop of about (3.3-2.4)=0.9 volts when conducting current. This level shifting transistor 20 will limit the voltage swing applied to the gates of transistors 70 and 40 as well as limiting the drain to source voltage of transistors 10 and 30 to approximately 2.4 volts. Similarly, transistors 50 and 60 prevent the full 3.3 volt swing on output 80 from appearing directly across transistors 40 and 70 respectively.
A problem with this interface circuit is that when the output 7 of the low voltage logic is high, the transistor 10 does not completely turn off. This is because the transistor 10 was fabricated on the basis of a 2.4 volt logic device and will have a relatively low threshold voltage magnitude (approximately 0.5 volts) whereas the applied gate to source voltage magnitude is approximately (3.3-2.4)=0.9, in this case. When the transistor 10 does not completely turn off, leakage current flows through transistor 10 and unnecessarily dissipates power. When too much current flows through transistor 10, the logic state of the signal driving gates 40 and 70 will be affected so that those devices are not fully switched off and on respectively. One solution to such a problem might be to change the device characteristics of the P channel transistor 10 such that the transistor turns off at the lower voltage signal level. The problem with this solution is that adjusting device characteristics typically requires a process change which is expensive and requires a long lead time. A similar prior art solution which has similar problems is to use a different type of device, such as a JFET, in place of transistor 10. The leakage problem might also arise even if the low voltage and high voltage device characteristics were identical when the tolerance on the logic input voltage is sufficient to affect the operation of the transistors. In this situation, process changes are not effective in fixing the leakage problem.